Power Aware Synthesis of Power Gated FSM
نویسندگان
چکیده
Power gating is often used to reduce power of a system which is in the form of a finite state machine (FSM). Power gating can be applied to turn OFF the inactive sub-machine which is obtained after partitioning the FSM by gating the supply voltage. Adjustment of supply voltage of one submachine for ON to OFF or OFF to ON state needs time, called wakeup time which affects the partitioning of FSMs for its power gated implementation as both the sub-machines are ON during this time. In this paper, we have calculated this wakeup time to find the number of clock cycles needed to activate the sub-machine. Power model based on state probability has been developed for the power-gated design of FSM. As effective partitioning and encoding of FSM decides the power consumption of final power gating implementation, in this paper Genetic Algorithm (GA) has been used to solve this integrated problem of both bi-partitioning and encoding. Experimental results obtained show the effectiveness of this approach. Affects of size of sleep transistor and sub-machine on the boundary depth have also been studied.
منابع مشابه
Low power finite state machine synthesis using power-gating
Power-gating turns off the power supply of a portion of the circuit completely, resulting in total elimination of power consumption for that part. However, it also necessitates that the sub-circuit to be activated should be charged for some time before its activation. This critical issue can influence the decomposition of a finite state machine (FSM) for its power gated implementation. In this ...
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